模拟CMOS集成电路设计 第2版pdf电子书版本下载

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1 Introduction to Analog Design 1

1.1 Why Analog? 1

1.1.1 Sensing and Processing Signals 1

1.1.2 When Digital Signals Become Analog 2

1.1.3 Analog Design Is in Great Demand 3

1.1.4 Analog Design Challenges 4

1.2 Why Integrated? 4

1.3 Why CMOS? 5

1.4 Why This Book? 5

1.5 Levels of Abstraction 5

2 Basic MOS Device Physics 7

2.1 General Considerations 8

2.1.1 MOSFET as a Switch 8

2.1.2 MOSFET Structure 8

2.1.3 MOS Symbols 9

2.2 MOS I/V Characteristics 10

2.2.1 Threshold Voltage 10

2.2.2 Derivation of I/V Characteristics 12

2.2.3 MOS Transconductance 19

2.3 Second-Order Effects 20

2.4 MOS Device Models 26

2.4.1 MOS Device Layout 26

2.4.2 MOS Device Capacitances 27

2.4.3 MOS Small-Signal Model 31

2.4.4 MOS SPICE models 34

2.4.5 NMOS Versus PMOS Devices 35

2.4.6 Long-Channel Versus Short-Channel Devices 35

2.5 Appendix A: FinFETs 36

2.6 Appendix B: Behavior of a MOS Device as a Capacitor 37

3 Single-Stage Amplifiers 45

3.1 Applications 45

3.2 General Considerations 45

3.3 Common-Source Stage 47

3.3.1 Common-Source Stage with Resistive Load 47

3.3.2 CS Stage with Diode-Connected Load 52

3.3.3 CS Stage with Current-Source Load 58

3.3.4 CS Stage with Active Load 59

3.3.5 CS Stage with Triode Load 60

3.3.6 CS Stage with Source Degeneration 61

3.4 Source Follower 68

3.5 Common-Gate Stage 75

3.6 Cascode Stage 82

3.6.1 Folded Cascode 90

3.7 Choice of Device Models 92

4 Differential Amplifiers 100

4.1 Single-Ended and Differential Operation 100

4.2 Basic Differential Pair 103

4.2.1 Qualitative Analysis 104

4.2.2 Quantitative Analysis 106

4.2.3 Degenerated Differential Pair 116

4.3 Common-Mode Response 118

4.4 Differential Pair with MOS Loads 123

4.5 Gilbert Cell 126

5 Current Mirrors and Biasing Techniques 134

5.1 Basic Current Mirrors 134

5.2 Cascode Current Mirrors 139

5.3 Active Current Mirrors 146

5.3.1 Large-Signal Analysis 149

5.3.2 Small-Signal Analysis 152

5.3.3 Common-Mode Properties 156

5.3.4 Other Properties of Five-Transistor OTA 159

5.4 Biasing Techniques 160

5.4.1 CS Biasing 161

5.4.2 CG Biasing 164

5.4.3 Source Follower Biasing 165

5.4.4 Differential Pair Biasing 166

6 Frequency Response of Amplifiers 173

6.1 General Considerations 173

6.1.1 Miller Effect 174

6.1.2 Association of Poles with Nodes 179

6.2 Common-Source Stage 180

6.3 Source Followers 188

6.4 Common-Gate Stage 193

6.5 Cascode Stage 196

6.6 Differential Pair 198

6.6.1 Differential Pair with Passive Loads 198

6.6.2 Differential Pair with Active Load 201

6.7 Gain-Bandwidth Trade-Offs 203

6.7.1 One-Pole Circuits 204

6.7.2 Multi-Pole Circuits 205

6.8 Appendix A: Extra Element Theorem 206

6.9 Appendix B: Zero-Value Time Constant Method 208

6.10 Appendix C: Dual of Miller's Theorem 212

7 Noise 219

7.1 Statistical Characteristics of Noise 219

7.1.1 Noise Spectrum 221

7.1.2 Amplitude Distribution 224

7.1.3 Correlated and Uncorrelated Sources 225

7.1.4 Signal-to-Noise Ratio 226

7.1.5 Noise Analysis Procedure 227

7.2 Types of Noise 228

7.2.1 Thermal Noise 228

7.2.2 Flicker Noise 234

7.3 Representation of Noise in Circuits 236

7.4 Noise in Single-Stage Amplifiers 243

7.4.1 Common-Source Stage 244

7.4.2 Common-Gate Stage 249

7.4.3 Source Followers 253

7.4.4 Cascode Stage 254

7.5 Noise in Current Mirrors 254

7.6 Noise in Differential Pairs 256

7.7 Noise-Power Trade-Off 263

7.8 Noise Bandwidth 264

7.9 Problem of Input Noise Integration 265

7.10 Appendix A: Problem of Noise Correlation 265

8 Feedback 274

8.1 General Considerations 274

8.1.1 Properties of Feedback Circuits 275

8.1.2 Types of Amplifiers 282

8.1.3 Sense and Return Mechanisms 284

8.2 Feedback Topologies 286

8.2.1 Voltage-Voltage Feedback 286

8.2.2 Current-Voltage Feedback 291

8.2.3 Voltage-Current Feedback 294

8.2.4 Current-Current Feedback 297

8.3 Effect of Feedback on Noise 298

8.4 Feedback Analysis Difficulties 299

8.5 Effect of Loading 303

8.5.1 Two-Port Network Models 303

8.5.2 Loading in Voltage-Voltage Feedback 304

8.5.3 Loading in Current-Voltage Feedback 308

8.5.4 Loading in Voltage-Current Feedback 310

8.5.5 Loading in Current-Current Feedback 313

8.5.6 Summary of Loading Effects 315

8.6 Bode's Analysis of Feedback Circuits 315

8.6.1 Observations 315

8.6.2 Interpretation of Coefficients 317

8.6.3 Bode's Analysis 320

8.6.4 Blackman'sImpedance Theorem 325

8.7 Middlebrook's Method 331

8.8 Loop Gain Calculation Issues 332

8.8.1 Preliminary Concepts 332

8.8.2 Difficulties with Return Ratio 334

8.9 Alternative Interpretations of Bode's Method 336

9 Operational Amplifiers 344

9.1 General Considerations 344

9.1.1 Performance Parameters 344

9.2 One-Stage Op Amps 349

9.2.1 Basic Topologies 349

9.2.2 Design Procedure 353

9.2.3 Linear Scaling 354

9.2.4 Folded-Cascode Op Amps 355

9.2.5 Folded-Cascode Properties 358

9.2.6 Design Procedure 359

9.3 Two-Stage Op Amps 361

9.3.1 Design Procedure 363

9.4 Gain Boosting 364

9.4.1 Basic Idea 364

9.4.2 Circuit Implementation 368

9.4.3 Frequency Response 371

9.5 Comparison 373

9.6 Output Swing Calculations 373

9.7 Common-Mode Feedback 374

9.7.1 Basic Concepts 374

9.7.2 CM Sensing Techniques 377

9.7.3 CM Feedback Techniques 380

9.7.4 CMFB in Two-Stage Op Amps 386

9.8 Input Range Limitations 388

9.9 Slew Rate 390

9.10 High-Slew-Rate Op Amps 397

9.10.1 One-Stage Op Amps 397

9.10.2 Two-Stage Op Amps 399

9.11 Power Supply Rejection 400

9.12 Noise in Op Amps 402

10 Stability and Frequency Compensation 410

10.1 General Considerations 410

10.2 Multipole Systems 414

10.3 Phase Margin 416

10.4 Basic Frequency Compensation 420

10.5 Compensation of Two-Stage Op Amps 426

10.6 Slewing in Two-Stage Op Amps 433

10.7 Other Compensation Techniques 436

10.8 Nyquist's Stability Criterion 439

10.8.1 Motivation 439

10.8.2 Basic Concepts 440

10.8.3 Construction of Polar Plots 442

10.8.4 Cauchy's Principle 447

10.8.5 Nyquist's Method 447

10.8.6 Systems with Poles at Origin 450

10.8.7 Systems with Multiple 180° Crossings 454

11 Nanometer Design Studies 459

11.1 Transistor Design Considerations 459

11.2 Deep-Submicron Effects 460

11.3 Transconductance Scaling 463

11.4 Transistor Design 466

11.4.1 Design for Given ID and VDs，min 466

11.4.2 Design for Given gm and ID 469

11.4.3 Design for Given gm and VDs，min 470

11.4.4 Design for a Given gm 471

11.4.5 Choice of Channel Length 472

11.5 Op Amp Design Examples 472

11.5.1 Telescopic Op Amp 473

11.5.2 Two-Stage Op Amp 487

11.6 High-Speed Amplifier 495

11.6.1 General Considerations 496

11.6.2 Op Amp Design 500

11.6.3 Closed-Loop Small-Signal Performance 501

11.6.4 Op Amp Scaling 502

11.6.5 Large-Signal Behavior 505

11.7 Summary 507

12 Bandgap References 509

12.1 General Considerations 509

12.2 Supply-Independent Biasing 509

12.3 Temperature-Independent References 513

12.3.1 Negative-TC Voltage 513

12.3.2 Positive-TC Voltage 514

12.3.3 Bandgap Reference 515

12.4 PTAT Current Generation 523

12.5 Constant-Gm Biasing 524

12.6 Speed and Noise Issues 525

12.7 Low-Voltage Bandgap References 529

12.8 Case Study 533

13 Introduction to Switched-Capacitor Circuits 539

13.1 General Considerations 539

13.2 Sampling Switches 543

13.2.1 MOSFETS as Switches 543

13.2.2 Speed Considerations 547

13.2.3 Precision Considerations 549

13.2.4 Charge Injection Cancellation 553

13.3 Switched-Capacitor Amplifiers 555

13.3.1 Unity-Gain Sampler/Buffer 555

13.3.2 Noninverting Amplifier 562

13.3.3 Precision Multiply-by-Two Circuit 567

13.4 Switched-Capacitor Integrator 568

13.5 Switched-Capacitor Common-Mode Feedback 571

14 Nonlinearity and Mismatch 576

14.1 Nonlinearity 576

14.1.1 General Considerations 576

14.1.2 Nonlinearity of Differential Circuits 579

14.1.3 Effect of Negative Feedback on Nonlinearity 581

14.1.4 Capacitor Nonlinearity 583

14.1.5 Nonlinearity in Sampling Circuits 584

14.1.6 Linearization Techniques 585

14.2 Mismatch 591

14.2.1 Effect of Mismatch 593

14.2.2 Offset Cancellation Techniques 598

14.2.3 Reduction of Noise by Offset Cancellation 602

14.2.4 Alternative Definition of CMRR 603

15 Layout and Packaging 607

15.1 General Layout Considerations 607

15.1.1 Design Rules 608

15.1.2 Antenna Effect 610

15.2 Analog Layout Techniques 610

15.2.1 Multifinger Transistors 611

15.2.2 Symmetty 613

15.2.3 Shallow Trench Isolation Issues 617

15.2.4 Well Proximity Effects 618

15.2.5 Reference Distribution 618

15.2.6 Passive Devices 620

15.2.7 Interconnects 627

15.2.8 Pads and ESD Protection 631

15.3 Substrate Coupling 634

15.4 Packaging 638