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1 Digital Systems and VLSI 1

1．1 Why Design Integrated Circuits? 1

1．2 Integrated Circuit Manufacturing 3

1．2．1 Technology 3

1．2．2 Economics 6

1．3 CMOS Technology 15

1．3．1 CMOS Circuit Techniques 15

1．3．2 Power Consumption 16

1．3．3 Design and Testability 17

1．4 Integrated Circuit Design Techniques 18

1．4．1 Hierarchical Design 19

1．4．2 Design Abstraction 22

1．4．3 Computer-Aided Design 28

1．5 A Look into the Future 30

1．6 Summary 31

1．7 References 31

1．8 Problems 32

2 Transistors and Layout 33

2．1 Introduction 33

2．2 Fabrication Processes 34

2．2．1 Overview 34

2．2．2 Fabrication Steps 36

2．3 Transistors 39

2．3．1 Structure of the Transistor 39

2．3．2 A Simple Transistor Model 44

2．3．3 Transistor Parasitics 47

2．3．4 Tub Ties and Latchup 48

2．3．5 Advanced Transistor Characteristics 52

2．3．6 Advanced Transistor Structures 60

2．3．7 Spice Models 61

2．4 Wires and Vias 63

2．4．1 Wire Parasitics 65

2．5 Design Rules 71

2．5．1 Fabrication Erros 72

2．5．2 Scalable Design Rules 74

2．5．3 SCMOS Design Rules 75

2．5．4 Typical Process Parameters 79

2．6．1 Layouts for Circuits 81

2．6 Layout Design and Tools 81

2．6．2 Stick Diagrams 84

2．6．3 Hierarchical Stick Diagrams 86

2．6．4 Layout Design and Analysis Tools 91

2．6．5 Automatic Layout 95

2．7 References 98

2．8 Problems 99

3 Logic Gates 107

3．1 Introduction 107

3．2 Combinational Logic Functions 107

3．3 Static Complementary Gates 110

3．3．1 Gate Structures 110

3．3．2 Basic Gate Layout 115

3．3．3 Logic Levels 119

3．3．4 Delay 121

3．3．5 Power Consumption 129

3．3．6 The Speed-Power Product 133

3．3．7 Layout and Parasitics 133

3．3．8 Driving Large Loads 137

3．4． Wires and Delay 138

3．4．1 Elmore Delay Model 138

3．4．2 Wire Sizing 139

3．4．3 RC Trees 141

3．5 Switch Logic 143

3．6 Alternative Gate Circuits 145

3．6．1 Pseudo-nMOS Logic 146

3．6．2 DCVS Logic 149

3．6．3 Domino Logic 150

3．7 References 155

3．8 Problems 156

4 Combinational Logic Networks 161

4．1 Introduction 161

4．2 Layout Design Methods 161

4．2．1 Single-Row Layout Design 162

4．2．2 Standard Cell Layout Design 171

4．3 Simulation 174

4．4 Combinational Network Delay 177

4．4．1 Fanout 178

4．4．2 Path Delay 180

4．4．3 Transistor Sizing 184

4．4．4 Automated Logic Optimization 188

4．5 Crosstalk 189

4．6 Power Optimization 195

4．7 Switch Logic Networks 199

4．8 Combinational Logic Testing 203

4．8．1 Gate Testing 205

4．8．2 Combinational Networks Testing 208

4．9 References 210

4．10 Problems 210

5 Sequential Machines 215

5．1 Introduction 215

5．2 Latches and Flip-Flops 215

5．2．1 Categories of Memory Elements 215

5．2．2 Latches 217

5．2．3 Flip-Flops 224

5．3 Sequential Systems and Clocking Disciplines 226

5．3．1 One-Phase Systems for Flip-Flops 229

5．3．2 Two-Phase Systems for Latches 229

5．3．3 Advanced Clocking Analysis 239

5．3．4 Clock Generation 246

5．4 Sequential System Design 247

5．4．1 Structural Specification of Sequential Machines 247

5．4．2 State Transition Graphs and Tables 249

5．4．3 State Assignment 258

5．5 Power Optimization 264

5．6 Design Validation 265

5．7 Sequential Testing 267

5．8 References 274

5．9 Problems 275

6 Subsystem Design 277

6．1 Introduction 277

6．2 Subsystem Design Principles 279

6．2．1 Pipelinig 279

6．2．2 Data Paths 281

6．3 Combinational Shifters 285

6．4 Adders 287

6．5 ALUs 296

6．6 Multipliers 297

6．7 High、Density Memory 306

6．7．1 ROM 308

6．7．2 Static RAM 309

6．7．3 The Three-Transistor Dynamic RAM 313

6．7．4 The One-Transistor Dynamic RAM 314

6．8 Field-Programmable Gate Arrays 318

6．9 Programmable Logic Arrays 318

6．10 References 322

6．11 Problems 323

7 Floorplanning 325

7．1 Introduction 325

7．2 Floorplanning Methods 325

7．2．1 Block Placement and Channel Definition 329

7．2．2 Global Routing 334

7．2．3 Switchbox Routing 336

7．2．4 Power Distribution 337

7．2．5 Clock Distribution 340

7．2．6 Floorplanning Tips 345

7．2．7 Design Validation 346

7．3 Off-Chip Connections 347

7．3．1 Packages 347

7．3．2 The I/O Architecture 351

7．3．3 Pad Design 352

7．4 References 356

7．5 Problems 357

8 Architecture Design 363

8．1 Introduction 363

8．2 Register-Transfer Design 364

8．2．1 Register-Transfer Simulation Programs 365

8．2．2 Data Path-Controller Architectures 367

8．2．3 ASM Chart Design 368

8．3 High-Level Synthesis 377

8．3．1 Functional Modeling Programs 379

8．3．2 Data 380

8．3．3 Control 390

8．3．4 Data and Control 397

8．3．5 Design Methodology 399

8．4 Architectures for Low Power 400

8．4．1 Architecture-Driven Voltage Scaling 400

8．4．2 Power-Down Modes 402

8．5 Architecture Testing 403

8．7 Problems 407

8．6 References 407

9 Chip Design 411

9．1 Introduction 411

9．2 Design Methodologies 411

9．3 Kitchen Timer Chip 419

9．3．1 Timer Specification and Architecture 420

9．3．2 Architecture Design 422

9．3．3 Logic and Layout Design 427

9．3．4 Design Validation 435

9．4 PDP-8 Data Path 437

9．4．1 PDP-8 Instruction Set 438

9．4．2 Register-Transfer Design 442

9．4．3 Clocking and Bus Desing 444

9．4．4 Logic and Layout Design 447

9．5 References 451

9．6 Problems 452

10 CAD Systems and Algorithms 453

10．1 Introduction 453

10．2 CAD Systems 454

10．3 Simulation 455

10．3．1 Event-Driven Simulation 455

10．3．2 Switch Simulation 457

10．4 Layout Synthesis 459

10．4．1 Placement 460

10．4．2 Global Routing 463

10．4．3 Detailed Routing 465

10．5 Layout Analysis 468

10．6 Timing Analysis and Optimization 470

10．7 Logic Synthesis 474

10．7．1 Technology-Independent Logic Optimization 476

10．7．2 Technology-Dependent Logic Optimizations 483

10．8 Test Generation 486

10．9 Sequential Machine Optimizations 488

10．10 Scheduling and Binding 490

10．11 Hardware/Software Co-Design 492

10．12 References 493

10．13 Problems 493

Appendix A: A Chip Designer s Lexicon 499

Appendix B: Chip Design Projects 511

B.1 Class Project Ideas 511

B.2 Project Proposal and Specification 513

B.3 Design Plan 514

B.4 Design Checkpoints and Documentation 517

B.4.1 Subsystems Check 517

B.4.2 First Layout Check 517

B.4.3 Project Completion 517

Appendix C: Design Modeling 519

C．1Introduction 519

C．2 Hardware Modeling in VHDL 519

C．3 Hardware Modeling in C 525

C．3．1 Simulator 528

C．3．2 Sample Execution 533

References 537

Index 551