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Chapter 1. Introduction to PLLs 1

1.1 Operating Priciples of the PLL 1

1.2 Classification of PLL Types 5

Chapter 2. Mixed-Signal PLLs 7

2.1 Block Diagram of the Mixed-Signal PLL 7

2.2 A Note on Phase Signals 8

2.3 Building Blocks of Mixed-Signal PLLs 11

2.3.1 Phase Detectors 11

2.3.2 Loop Filters (First Order) 23

2.3.3 Controlled Oscillators 26

2.3.4 Down-Scalers 29

2.4 PLL Performance in the Locked State 29

2.4.1 Mathematical Model for the Locked State 30

2.4.2 Definition of Transfer Functions 31

2.4.3 Transient Response of the PLL in the Locked State 36

2.4.4 Steady-State Error of the PLL 39

2.5 The Order of the PLL System 41

2.5.1 Number of Poles 41

2.5.2 A Special Case: The First-Order PLL 42

2.6 PLL Performance in the Unlocked State 42

2.6.1 Mathematical Model for the Unlocked State 42

2.6.2 Key Parameters of the PLL 51

2.7 Phase Detectors with Charge Pump Output 73

2.8 PLL Performance in the Presence of Noise 80

2.8.1 Sources and Types of Noise in a PLL 80

2.8.2 Defining Noise Parameters 82

2.8.3 The Impact of Noise on PLL Performance 83

2.8.4 Pull-in Techniques for Noisy Signals 91

2.9 Design Procedure for Mixed-Signal PLLs 93

2.10 Mixed-Signal PLL Applications 102

2.10.1 Retiming and Clock Signal Recovery 102

2.10.2 Motor-Speed Control 109

Chapter 3. PLL Frequency Synthesizers 115

3.1 Synthesizers in Wireless and RF Applications 115

3.2 PLL Synthesizer Fundamentals 116

3.2.1 Integer-N Frequency Synthesizers 116

3.2.2 Case Study: Designing an Integer-N PLL Frequency Synthesizer 123

3.2.3 Fractional-N Frequency Synthesizers 127

3.3 Single-Loop and Multiloop Frequency Synthesizers 132

3.4 Noise in Frequency Synthesizers 134

3.4.1 Phase Jitter??n,ref of the Reference Oscillator 136

3.4.2 Phase Jitter??n,vco of the VCO 144

3.4.3 Reference Feedthrough Created by the Phase Detector 145

Chapter 4. Higher-Order Loops 151

4.1 Motivation for Higher-Order Loops 151

4.2 Analyzing Stability of Higher-Order Loops 151

4.3 Designing Third-Order PLLs 155

4.3.1 Passive Lead-Lag Loop Filter 155

4.3.2 Active Lead-Lag Loop Filter 157

4.3.3 Active PI Loop Filter 159

4.4 Designing Fourth-Order PLLs 162

4.4.1 Active Lead-Lag Loop Filter 162

4.4.2 Active PI Loop Filter 165

4.5 Designing Fifth-Order PLLs 168

4.5.1 Active Lead-Lag Loop Filter 168

4.5.2 Active PI Loop Filter 172

4.6 The Key Parameters of Higher-Order PLLs 176

4.7 Loop Filters for Phase Detectors with Charge Pump Output 177

4.7.1 Loop Filters for Second-Order PLLs 177

4.7.2 Loop Filters for Third-Order PLLs 178

4.7.3 Loop Filters for Fourth-Order PLLs 179

4.7.4 Loop Filters for Fifth-Order PLLs 180

Chapter 5. Computer-Aided Design and Simulation of Mixed-Signal PLLs 181

5.1 Overview 181

5.2 Quick Tour 182

5.2.1 Configuring the PLL System 182

5.2.2 Designing the Loop Filter 184

5.2.3 Analyzing Stability of the Loop 186

5.2.4 Getting the Loop Filter Schematic 188

5.2.5 Running Simulations 190

5.2.6 Getting Help 193

5.2.7 Shaping the Appearance of Graphic Objects 193

5.3 Case study: Design and Simulation of a Second-Order PLL 194

5.4 Suggestions for Other Case Studies 201

5.5 Displaying Waveforms of Tristate Signals 202

Chapter 6. All-Digital PLLs (ADPLLs) 205

6.1 ADPLL Components 205

6.1.1 All-Digital Phase Detectors 205

6.1.2 All-Digital Loop Filters 211

6.1.3 Digital-Controlled Oscillators 216

6.2 Examples of Implemented ADPLLs 221

6.2.1 ADPLL Example 1 221

6.2.2 ADPLL Example 2 225

6.2.3 ADPLL Example 3 227

6.3 Theory of a Selected Type of ADPLL 228

6.3.1 Effects of Discrete-Time Operation 228

6.3.2 The Hold Range of the ADPLL 234

6.3.3 Frequency-Domain Analysis of the ADPLL 237

6.3.4 Ripple Reduction Techniques 239

6.3.5 Higher-Order ADPLLs 240

6.4 Typical ADPLL Applications 241

6.5 Designing an ADPLL 243

6.5.1 Case Study: Designing an ADPLL FSK Decoder 243

Chapter 7. Computer-Aided Design and Simulation of ADPLLs 247

7.1 Setting up the Design Parameters 247

7.2 Simulating ADPLL Performance 249

7.3 Case Studies of ADPLL Behavior 250

Chapter 8. The Software PLL (SPLL) 257

8.1 The Hardware-Software Tradeoff 257

8.2 Feasibility of an SPLL Design 258

8.3 SPLL Examples 259

8.3.1 An LPLL-like SPLL 260

8.3.2 A DPLL-like SPLL 266

8.3.3 A Note on ADPLL-like SPLLs 275

Chapter 9. The PLL in Communications 277

9.1 Types of Communications 277

9.1.1 From Analog to Digital 277

9.2 Digital Communications by Bandpass Modulation 279

9.2.1 Amplitude Shift Keying 279

9.2.2 Phase Shift Keying 280

9.2.3 Quadrature Phase Shift Keying 281

9.2.4 QAM (m-ary Phase Shift Keying) 282

9.2.5 Frequency Shift Keying 284

9.3 The Role of Synchronization in Digital Communications 285

9.4 Digital Communications Using BPSK 286

9.4.1 Transmitter Considerations 286

9.4.2 Receiver Considerations 291

9.5 Digital Communications Using QPSK 301

9.5.1 Transmitter Considerations 301

9.5.2 Receiver Considerations 303

9.6 Digital Communications Using QAM 306

9.7 Digital Communications Using FSK 307

9.7.1 Simple FSK Decoders: Easy to Implement, but Not Effective 307

9.7.2 Coherent FSK Detection 308

9.7.3 Noncoherent FSK Detection and Quadrature FSK Decoders 310

Chapter 10. State of the Art of Commercial PLL Integrated Circuits 311

Chapter 11. Measuring PLL Parameters 327

11.1 Measurement of Center Frequency fo 327

11.2 Measurement of VCO Gain Ko 328

11.3 Measurement of Phase-Detector Gain Kd 329

11.4 Measurement of Hold Range??h and Pull-in Range?? 331

11.5 Measurement of Natural Frequency?? Damping Factor??, and Lock Range?? 334

11.6 Measurement of the Phase-Transfer Function H(??) and the 3-dB Bandwidth??3dB 337

Appendix A. The Pull-in Process 341

A.1 Simplified Model for the Pull-in Range?? of the LPLL 341

A.2 Simplified Model for the Pull-in Time TP of the LPLL 348

A.3 The Pull-in Range?? of the DPLL 352

A.4 The Pull-in Time TP of the DPLL 353

Appendix B. The Laplace Transform 355

B.1 Transforms Are the Engineer's Tools 355

B.2 A Laplace Transform Is the Key to Success 359

B.3 A Numerical Example of the Laplace Transform 362

B.4 Some Basic Properties of the Laplace Transform 363

B.4.1 Addition Theorem 363

B.4.2 Multiplication by a Constant Factor k 363

B.4.3 Multiplication of Signals 363

B.4.4 Delay in the Time Domain 367

B.4.5 Differentiation and Integration in the Time Domain 368

B.4.6 The initial- and Final-Value Theorems 371

B.5 Using the Table of Laplace Transforms 372

B.6 Applying the Laplace Transform to Electric Networks 373

B.7 Closing the Gap between the Time Domain and the Complex-Frequency Domain 376

B.8 Networks with Nonzero Stored Energy at t = 0 377

B.9 Analyzing Dynamic Performance by the Pole-Zero Plot 379

B.10 A Simple Physical Interpretation of "Complex Frequency" 382

Appendix C. Digital Filter Basics 385

C.1 The Transfer Function H(z) of Digital Filters 385

C.2 IIR Filters 388

C.2.1 The Impulse-Invariant z Transform 388

C.2.2 The Bilinear z Transform 395

C.3 FIR Filters 399

C.3.1 Window-FIR Filters 404

C.3.2 Designing FIR filters with the Parks-McClellan Algorithm 408

References 415

Index 417