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1 Digital Systems and VLSI 1

1.1 Why Design Integrated Circuits? 1

1.2 Integrated Circuit Manufacturing 4

1.2.1 Technology 4

1.2.2 Economics 6

1.3 CMOS Technology 15

1.3.1 CMOS Circuit Techniques 15

1.3.2 Power Consumption 16

1.3.3 Design and Testability 17

1.4 Integrated Circuit Design Techniques 18

1.4.1 Hierarchical Design 19

1.4.2 Design Abstraction 22

1.4.3 Computer-Aided Design 28

1.5 A Look into the Future 30

1.6 Summary 31

1.7 References 31

1.8 Problems 32

2 Transistors and Layout 33

2.1 Introduction 33

2.2 Fabrication Processes 34

2.2.1 Overview 34

2.2.2 Fabrication Steps 37

2.3 Transistors 40

2.3.1 Structure of the Transistor 40

2.3.2 A Simple Transistor Model 45

2.3.3 Transistor Parasitics 48

2.3.4 Tub Ties and Latchup 50

2.3.5 Advanced Transistor Characteristics 53

2.3.6 Leakage and Subthreshold Currents 60

2.3.7 Advanced Transistor Structures 61

2.3.8 Spice Models 61

2.4 Wires and Vias 62

2.4.1 Wire Parasitics 65

2.4.2 Skin Effect in Copper Interconnect 72

2.5 Design Rules 74

2.5.1 Fabrication Errors 75

2.5.2 Scalable Design Rules 77

2.5.3 SCMOS Design Rules 79

2.5.4 Typical Process Parameters 83

2.6 Layout Design and Tools 83

2.6.1 Layouts for Circuits 83

2.6.2 Stick Diagrams 88

2.6.3 Hierarchical Stick Diagrams 90

2.6.4 Layout Design and Analysis Tools 95

2.6.5 Automatic Layout 99

2.7 References 102

2.8 Problems 102

3 Logic Gates 111

3.1 Introduction 111

3.2 Combinational Logic Functions 112

3.3 Static Complementary Gates 114

3.3.1 Gate Structures 115

3.3.2 Basic Gate Layouts 118

3.3.3 Logic Levels 121

3.3.4 Delay and Transition Time 126

3.3.5 Power Consumption 135

3.3.6 The Speed-Power Product 138

3.3.7 Layout and Parasitics 139

3.3.8 Driving Large Loads 142

3.4 Switch Logic 143

3.5 Alternative Gate Circuits 144

3.5.1 Pseudo-nMOS Logic 145

3.5.2 DCVS Logic 147

3.5.3 Domino Logic 149

3.6 Low-Power Gates 154

3.7 Delay Through Resistive Interconnect 160

3.7.1 Delay Through an RC Transmission Line 160

3.7.2 Delay Through RC Trees 163

3.7.3 Buffer Insertion in RC Transmission Lines 167

3.7.4 Crosstalk Between RC Wires 169

3.8 Delay Through Inductive Interconnect 172

3.8.1 RLC Basics 173

3.8.2 RLC Transmission Line Delay 174

3.8.3 Buffer Insertion in RLC Transmission Lines 175

3.9 References 177

3.10 Problems 179

4 Combinational Logic Networks 185

4.1 Introduction 185

4.2 Standard Cell-Based Layout 186

4.2.1 Single-Row Layout Design 187

4.2.2 Standard Cell Layout Design 196

4.3 Simulation 198

4.4 Combinational Network Delay 202

4.4.1 Fanout 203

4.4.2 Path Delay 204

4.4.3 Transistor Sizing 209

4.4.4 Automated Logic Optimization 218

4.5 Logic and Interconnect Design 219

4.5.1 Delay Modeling 220

4.5.2 Wire Sizing 221

4.5.3 Buffer Insertion 222

4.5.4 Crosstalk Minimization 224

4.6 Power Optimization 229

4.6.1 Power Analysis 229

4.7 Switch Logic Networks 233

4.8 Combinational Logic Testing 237

4.8.1 Gate Testing 239

4.8.2 Combinational Network Testing 242

4.9 References 244

4.10 Problems 244

5 Sequential Machines 249

5.1 Introduction 249

5.2 Latches and Flip-Flops 250

5.2.1 Categories of Memory Elements 250

5.2.2 Latches 252

5.2.3 Flip-Flops 259

5.3 Sequential Systems and Clocking Disciplines 260

5.3.1 One-Phase Systems for Flip-Flops 263

5.3.2 Two-Phase Systems for Latches 265

5.3.3 Advanced Clocking Analysis 273

5.3.4 Clock Generation 280

5.4.1 Structural Specification of Sequential Machines 281

5.4 Sequential System Design 281

5.4.2 State Transition Graphs and Tables 283

5.4.3 State Assignment 292

5.5 Power Optimization 298

5.6 Design Validation 299

5.7 Sequential Testing 301

5.8 References 308

5.9 Problems 308

6 Subsystem Design 311

6.1 Introduction 311

6.2 Subsystem Design Principles 314

6.2.1 Pipelining 314

6.2.2 Data Paths 316

6.3 Combinational Shifters 319

6.4 Adders 322

6.5 ALUs 329

6.6 Multipliers 330

6.7 High-Density Memory 339

6.7.1 ROM 341

6.7.2 Static RAM 343

6.7.3 The Three-Transistor Dynamic RAM 347

6.7.4 The One-Transistor Dynamic RAM 348

6.8 Field-Programmable Gate Arrays 351

6.9 Programmable Logic Arrays 352

6.10 References 356

6.11 Problems 356

7 Floorplanning 359

7.1 Introduction 359

7.2 Floorplanning Methods 360

7.2.1 Block Placement and Channel Definition 364

7.2.2 Global Routing 370

7.2.3 Switchbox Routing 372

7.2.4 Power Distribution 373

7.2.5 Clock Distribution 376

7.2.6 Floorplanning Tips 381

7.2.7 Design Validation 382

7.3 Off-Chip Connections 383

7.3.1 Packages 383

7.3.2 The I/O Architecture 387

7.3.3 Pad Design 388

7.4 References 391

7.5 Problems 393

8.1 Introduction 399

8 Architecture Design 399

8.2 Hardware Description Languages 400

8.2.1 Modeling with Hardware Description Languages 400

8.2.2 VHDL 405

8.2.3 Verilog 414

8.2.4 C as a Hardware Description Language 421

8.3 Register-Transfer Design 422

8.3.1 Data Path-Controller Architectures 424

8.3.2 ASM Chart Design 425

8.4 High-Level Synthesis 434

8.4.1 Functional Modeling Programs 436

8.4.2 Data 437

8.4.3 Control 447

8.4.4 Data and Control 453

8.4.5 Design Methodology 455

8.5 Architectures for Low Power 456

8.5.1 Architecture-Driven Voltage Scaling 457

8.5.2 Power-Down Modes 458

8.6 Systems-on-Chips and Embedded CPUs 459

8.7 Architecture Testing 465

8.8 References 469

8.9 Problems 469

9 Chip Design 473

9.1 Introduction 473

9.2 Design Methodologies 473

9.3 Kitchen Timer Chip 482

9.3.1 Timer Specification and Architecture 483

9.3.2 Architecture Design 485

9.3.3 Logic and Layout Design 490

9.3.4 Design Validation 497

9.4 Microprocessor Data Path 500

9.4.1 Data Path Organization 501

9.4.2 Clocking and Bus Design 502

9.4.3 Logic and Layout Design 504

9.5 References 506

9.6 Problems 507

10 CAD Systems and Algorithms 509

10.1 Introduction 510

10.2 CAD Systems 510

10.3 Switch-Level Simulation 511

10.4 Layout Synthesis 513

10.4.1 Placement 515

10.4.2 Global Routing 518

10.4.3 Detailed Routing 520

10.5 Layout Analysis 522

10.6 Timing Analysis and Optimization 524

10.7 Logic Synthesis 529

10.7.1 Technology-Independent Logic Optimization 530

10.7.2 Technology-Dependent Logic Optimizations 537

10.8 Test Generation 540

10.9 Sequential Machine Optimizations 542

10.10 Scheduling and Binding 544

10.11 Hardware/Software Co-Design 546

10.12 References 547

10.13 Problems 547

A Chip Designer's Lexicon 553

B Chip Design Projects 571

B.1 Class Project Ideas 571

B.2 Project Proposal and Specification 572

B.3 Design Plan 573

B.4 Design Checkpoints and Documentation 576

B.4.1 Subsystems Check 577

B.4.2 First Layout Check 577

B.4.3 Project Completion 577

C Kitchen Timer Model 579

C.1 Hardware Modeling in C 579

C.1.1 Simulator 581

C.1.2 Sample Execution 587

Index 607