现代VLSI设计 片上系统设计 第3版 改编版pdf电子书版本下载

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1 Digital Systems and VLSI 1

1.1 Why Design Integrated Circuits? 1

1.2 Integrated Circuit Manufacturing 4

1.2.1 Technology 4

1.2.2 Economics 6

1.3 CMOS Technology 15

1.3.1 CMOS Circuit Techniques 15

1.3.2 Power Consumption 16

1.3.3 DesignandTestability 17

1.4 Integrated Circuit Design Techniques 18

1.4.1 Hierarchical Design 19

1.4.2 Design Abstraction 22

1.4.3 Computer-Aided Design 28

1.5 ALook into the Future 30

1.6 Summary 31

1.7 References 31

1.8 Problems 32

2 Transistors and Layout 33

2.1 Introduction 33

2.2 Fabrication Processes 34

2.2.1 Overview 34

2.2.2 Fabrication Steps 37

2.3 Transistors 40

2.3.1 Structure of the Transistor 40

2.3.2 A Simple Transistor Model 45

2.3.3 Transistor Parasitics 48

2.3.4 Tub Ties and Latchup 50

2.3.5 Advanced Transistor Characteristics 53

2.3.6 Leakage and Subthreshold Currents 60

2.3.7 Advanced Transistor Structures 61

2.3.8 Spice Models 61

2.4 Wires and Vias 62

2.4.1 Wire Parasitics 65

2.4.2 Skin Effect in Copper Interconnect 72

2.5 Design Rules 74

2.5.1 Fabrication Errors 75

2.5.2 Scalable Design Rules 77

2.5.3 SCMOS Design Rules 79

2.5.4 Typical Process Parameters 83

2.6 Layout Design and Tools 83

2.6.1 Layouts for Circuits 83

2.6.2 Stick Diagrams 88

2.6.3 Layout Design and Analysis Tools 90

2.6.4 Automatic Layout 94

2.7 References 97

2.8 Problems 97

3 Logic Gates 105

3.1 Introduction 105

3.2 Static Complementary Gates 106

3.2.1 Gate Structures 106

3.2.2 Basic Gate Layouts 110

3.2.3 Logic Levels 113

3.2.4 Delay and Transition Time 118

3.2.5 Power Consumption 127

3.2.6 The Speed-Power Product 130

3.2.7 Layout and Parasitics 131

3.2.8 Driving Large Loads 134

3.3 Switch Logic 135

3.4 Alternative Gate Circuits 136

3.4.1 Pseudo-nMOS Logic 137

3.4.2 DCVS Logic 139

3.4.3 Domino Logic 141

3.5 Low-Power Gates 146

3.6 Delay Through Resistive Interconnect 152

3.6.1 Delay Through an RC Transmission Line 152

3.6.2 Delay Through RC Trees 155

3.6.3 Buffer Insertion in RC Transmission Lines 159

3.6.4 Crosstalk Between RC Wires 161

3.7 Delay Through Inductive Interconnect 164

3.7.1 RLC Basics 165

3.7.2 RLC Transmission Line Delay 166

3.7.3 Buffer Insertion in RLC Transmission Lines 167

3.8 References 169

3.9 Problems 171

4 Combinational Logic Networks 177

4.1 Introduction 177

4.2 Standard Cell-Based Layout 178

4.2.1 Single-Row Layout Design 179

4.2.2 Standard Cell Layout Design 188

4.3 Simulation 190

4.4 Combinational Network Delay 194

4.4.1 Fanout 195

4.4.2 Path Delay 196

4.4.3 Transistor Sizing 201

4.4.4 Automated Logic Optimization 210

4.5 Logic and Interconnect Design 211

4.5.1 Delay Modeling 212

4.5.2 Wire Sizing 213

4.5.3 Buffer Insertion 214

4.5.4 Crosstalk Minimization 216

4.6 Power Optimization 221

4.6.1 Power Analysis 221

4.7 Switch Logic Networks 225

4.8 Combinational Logic Testing 229

4.8.1 Gate Testing 231

4.8.2 Combinational Network Testing 234

4.9 References 236

4.10 Problems 236

5 Sequential Machines 241

5.1 Introduction 241

5.2 Latches and Flip-Flops 242

5.2.1 Categories of Memory Elements 242

5.2.2 Latches 244

5.2.3 Flip-Flops 251

5.3 Sequential Systems and Clocking Disciplines 252

5.3.1 One-Phase Systems for Flip-Flops 255

5.3.2 Two-Phase Systems for Latches 257

5.3.3 Advanced Clocking Analysis 265

5.3.4 Clock Generation 272

5.4 Sequential System Design 273

5.4.1 Structural Specification of Sequential Machines 273

5.4.2 State Transition Graphs and Tables 275

5.4.3 State Assignment 284

5.5 Power Optimization 290

5.6 Design Validation 291

5.7 Sequential Testing 293

5.8 References 300

5.9 Problems 300

6 Subsystem Design 303

6.1 Introduction 303

6.2 Subsystem Design Principles 306

6.2.1 Pipelining 306

6.2.2 Data Paths 308

6.3 Combinational Shifters 311

6.4 Adders 314

6.5 ALUs 321

6.6 Multipliers 322

6.7 High-Density Memory 331

6.7.1 ROM 333

6.7.2 Static RAM 335

6.7.3 The Three-Transistor Dynamic RAM 339

6.7.4 The One-Transistor Dynamic RAM 340

6.8 References 344

6.9 Problems 344

7 Floorplanning 347

7.1 Introduction 347

7.2 Floorplanning Methods 348

7.2.1 Block Placement and Channel Definition 352

7.2.2 Global Routing 358

7.2.3 Switchbox Routing 360

7.2.4 Power Distribution 361

7.2.5 Clock Distribution 364

7.2.6 Floorplanning Tips 369

7.2.7 Design Validation 370

7.3 Off-Chip Connections 371

7.3.1 Packages 371

7.3.2 The I/O Architecture 375

7.3.3 Pad Design 376

7.4 References 379

7.5 Problems 381

8 Architecture Design 387

8.1 Introduction 387

8.2 Hardware Description Languages 388

8.2.1 Modeling with Hardware Description Languages 388

8.2.2 VHDL 393

8.2.3 Verilog 402

8.2.4 C as a Hardware Description Language 409

8.3 Register-Transfer Design 410

8.3.1 Data Path-Controller Architectures 412

8.3.2 ASM ChartDesign 413

8.4 High-Level Synthesis 422

8.4.1 Functional Modeling Programs 424

8.4.2 Data 425

8.4.3 Control 435

8.4.4 Dataand Control 441

8.4.5 Design Methodology 443

8.5 Architectures for Low Power 444

8.5.1 Architecture-Driven Voltage Scaling 445

8.5.2 Power-Down Modes 446

8.6 Systems-on-Chips and Embedded CPUs 447

8.7 Architecture Testing 453

8.8 References 457

8.9 Problems 457

9 Chip Design 461

9.1 Introduction 461

9.2 Design Methodologies 461

9.3 Kitchen Timer Chip 470

9.3.1 Timer Specification and Architecture 471

9.3.2 Architecture Design 473

9.3.3 Logic and Layout Design 478

9.3.4 Design Validation 485

9.4 Microprocessor Data Path 488

9.4.1 Data Path Organization 489

9.4.2 Clocking and Bus Design 490

9.4.3 Logic and Layout Design 492

9.5 References 494

9.6 Problems 495

10 CAD Systems and Algorithms 497

10.1 Introduction 498

10.2 CAD Systems 498

10.3 Switch-Level Simulation 499

10.4 Layout Synthesis 501

10.4.1 Placement 503

10.4.2 Global Routing 506

10.4.3 Detailed Routing 508

10.5 Layout Analysis 510

10.6 Tuning Analysis and Optimization 512

10.7 Logic Synthesis 517

10.7.1 Technology-Independent Logic Optimization 518

10.7.2 Technology-Dependent Logic Optimizations 525

10.8 Test Generation 528

10.9 Sequential Machine Optimizations 530

10.10 Scheduling and Binding 532

10.11 Hardware/Software Co-Design 534

10.12 References 535

10.13 Problems 535

A Chip Designer's Lexicon 539

B Chip Design Projects 557

B.1 Class Project Ideas 557

B.2 Project Proposal and Specification 558

B.3 Design Plan 559

B.4 Design Checkpoints and Documentation 562

B.4.1 Subsystems Check 563

B.4.2 First Layout Check 563

B.4.3 Project Completion 563

C Kitchen Timer Model 565

C.1 Hardware Modeling in C 565

C.1.1 Simulator 567

C.1.2 Sample Execution 573

References 577

Index 593