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CHAPTER 1 INTRODUCTION TO RF AND WIRELESS TECHNOLOGY 1

1.1 A Wireless World 1

1.2 RF Design Is Challenging 3

1.3 The Big Picture 4

References 5

CHAPTER 2 BASIC CONCEPTS IN RF DESIGN 7

2.1 General Considerations 7

2.1.1 Units in RF Design 7

2.1.2 Time Variance 9

2.1.3 Nonlinearity 12

2.2 Effects of Nonlinearity 14

2.2.1 Harmonic Distortion 14

2.2.2 Gain Compression 16

2.2.3 Cross Modulation 20

2.2.4 Intermodulation 21

2.2.5 Cascaded Nonlinear Stages 29

2.2.6 AM/PM Conversion 33

2.3 Noise 35

2.3.1 Noise as a Random Process 36

2.3.2 Noise Spectrum 37

2.3.3 Effect of Transfer Function on Noise 39

2.3.4 Device Noise 40

2.3.5 Representation of Noise in Circuits 46

2.4 Sensitivity and Dynamic Range 58

2.4.1 Sensitivity 59

2.4.2 Dynamic Range 60

2.5 Passive Impedance Transformation 62

2.5.1 Quality Factor 63

2.5.2 Series-to-Parallel Conversion 63

2.5.3 Basic Matching Networks 65

2.5.4 Loss in Matching Networks 69

2.6 Scattering Parameters 71

2.7 Analysis of Nonlinear Dynamic Systems 75

2.7.1 Basic Considerations 75

2.8 Volterra Series 77

2.8.1 Method of Nonlinear Currents 81

References 86

Problems 86

CHAPTER 3 COMMUNICATION CONCEPTS 91

3.1 General Considerations 91

3.2 Analog Modulation 93

3.2.1 Amplitude Modulation 93

3.2.2 Phase and Frequency Modulation 95

3.3 Digital Modulation 99

3.3.1 Intersymbol Interference 101

3.3.2 Signal Constellations 105

3.3.3 Quadrature Modulation 107

3.3.4 GMSK and GFSK Modulation 112

3.3.5 Quadrature Amplitude Modulation 114

3.3.6 Orthogonal Frequency Division Multiplexing 115

3.4 Spectral Regrowth 118

3.5 Mobile RF Communications 119

3.6 Multiple Access Techniques 123

3.6.1 Time and Frequency Division Duplexing 123

3.6.2 Frequency-Division Multiple Access 125

3.6.3 Time-Division Multiple Access 125

3.6.4 Code-Division Multiple Access 126

3.7 Wireless Standards 130

3.7.1 GSM 132

3.7.2 IS-95 CDMA 137

3.7.3 Wideband CDMA 139

3.7.4 Bluetooth 143

3.7.5 IEEE802.11a/b/g 147

3.8 Appendix Ⅰ:Differential Phase Shift Keying 151

References 152

Problems 152

CHAPTER 4 TRANSCEIVER ARCHITECTURES 155

4.1 General Considerations 155

4.2 Receiver Architectures 160

4.2.1 Basic Heterodyne Receivers 160

4.2.2 Modern Heterodyne Receivers 171

4.2.3 Direct-Conversion Receivers 179

4.2.4 Image-Reject Receivers 200

4.2.5 Low-IF Receivers 214

4.3 Transmitter Architectures 226

4.3.1 General Considerations 226

4.3.2 Direct-Conversion Transmitters 227

4.3.3 Modern Direct-Conversion Transmitters 238

4.3.4 Heterodyne Transmitters 244

4.3.5 Other TX Architectures 248

4.4 OOK Transceivers 248

References 249

Problems 250

CHAPTER 5 LOW-NOISE AMPLIFIERS 255

5.1 General Considerations 255

5.2 Problem of Input Matching 263

5.3 LNA Topologies 266

5.3.1 Common-Source Stage with Inductive Load 266

5.3.2 Common-Source Stage with Resistive Feedback 269

5.3.3 Common-Gate Stage 272

5.3.4 Cascode CS Stage with Inductive Degeneration 284

5.3.5 Variants of Common-Gate LNA 296

5.3.6 Noise-Cancelling LNAs 300

5.3.7 Reactance-Cancelling LNAs 303

5.4 Gain Switching 305

5.5 Band Switching 312

5.6 High-IP2 LNAs 313

5.6.1 Differential LNAs 314

5.6.2 Other Methods of IP2 Improvement 323

5.7 Nonlinearity Calculations 325

5.7.1 Degenerated CS Stage 325

5.7.2 Undegenerated CS Stage 329

5.7.3 Differential and Quasi-Differential Pairs 331

5.7.4 Degenerated Differential Pair 332

References 333

Problems 333

CHAPTER 6 MIXERS 337

6.1 General Considerations 337

6.1.1 Performance Parameters 338

6.1.2 Mixer Noise Figures 343

6.1.3 Single-Balanced and Double-Balanced Mixers 348

6.2 Passive Downconversion Mixers 350

6.2.1 Gain 350

6.2.2 LO Self-Mixing 357

6.2.3 Noise 357

6.2.4 Input Impedance 364

6.2.5 Current-Driven Passive Mixers 366

6.3 Active Downconversion Mixers 368

6.3.1 Conversion Gain 370

6.3.2 Noise in Active Mixers 377

6.3.3 Linearity 387

6.4 Improved Mixer Topologies 393

6.4.1 Active Mixers with Current-Source Helpers 393

6.4.2 Active Mixers with Enhanced Transconductance 394

6.4.3 Active Mixers with High IP2 397

6.4.4 Active Mixers with Low Flicker Noise 405

6.5 Upconversion Mixers 408

6.5.1 Performance Requirements 408

6.5.2 Upconversion Mixer Topologies 409

References 424

Problems 425

CHAPTER 7 PASSIVE DEVICES 429

7.1 General Considerations 429

7.2 Inductors 431

7.2.1 Basic Structure 431

7.2.2 Inductor Geometries 435

7.2.3 Inductance Equations 436

7.2.4 Parasitic Capacitances 439

7.2.5 Loss Mechanisms 444

7.2.6 Inductor Modeling 455

7.2.7 Alternative Inductor Structures 460

7.3 Transformers 470

7.3.1 Transformer Structures 470

7.3.2 Effect of Coupling Capacitance 475

7.3.3 Transformer Modeling 475

7.4 Transmission Lines 476

7.4.1 T-Line Structures 478

7.5 Varactors 483

7.6 Constant Capacitors 490

7.6.1 MOS Capacitors 491

7.6.2 Metal-Plate Capacitors 493

References 495

Problems 496

CHAPTER 8 OSCILLATORS 497

8.1 Performance Parameters 497

8.2 Basic Principles 501

8.2.1 Feedback View of Oscillators 502

8.2.2 One-Port View of Oscillators 508

8.3 Cross-Coupled Oscillator 511

8.4 Three-Point Oscillators 517

8.5 Voltage-Controlled Oscillators 518

8.5.1 Tuning Range Limitations 521

8.5.2 Effect of Varactor Q 522

8.6 LC VCOs with Wide Tuning Range 524

8.6.1 VCOs with Continuous Tuning 524

8.6.2 Amplitude Variation with Frequency Tuning 532

8.6.3 Discrete Tuning 532

8.7 Phase Noise 536

8.7.1 Basic Concepts 536

8.7.2 Effect of Phase Noise 539

8.7.3 Analysis of Phase Noise:Approach Ⅰ 544

8.7.4 Analysis of Phase Noise:Approach Ⅱ 557

8.7.5 Noise of Bias Current Source 565

8.7.6 Figures of Merit of VCOs 570

8.8 Design Procedure 571

8.8.1 Low-Noise VCOs 573

8.9 LO Interface 575

8.10 Mathematical Model of VCOs 577

8.11 Quadrature Oscillators 581

8.11.1 Basic Concepts 581

8.11.2 Properties of Coupled Oscillators 584

8.11.3 Improved Quadrature Oscillators 589

8.12 Appendix Ⅰ:Simulation of Quadrature Oscillators 592

References 593

Problems 594

CHAPTER 9 PHASE-LOCKED LOOPS 597

9.1 Basic Concepts 597

9.1.1 Phase Detector 597

9.2 Type-Ⅰ PLLs 600

9.2.1 Alignment of a VCO's Phase 600

9.2.2 Simple PLL 601

9.2.3 Analysis of Simple PLL 603

9.2.4 Loop Dynamics 606

9.2.5 Frequency Multiplication 609

9.2.6 Drawbacks of Simple PLL 611

9.3 Type-Ⅱ PLLs 611

9.3.1 Phase/Frequency Detectors 612

9.3.2 Charge Pumps 614

9.3.3 Charge-Pump PLLs 615

9.3.4 Transient Response 620

9.3.5 Limitations of Continuous-Time Approximation 622

9.3.6 Frequency-Multiplying CPPLL 623

9.3.7 Higher-Order Loops 625

9.4 PFD/CP Nonidealities 627

9.4.1 UP and Down Skew and Width Mismatch 627

9.4.2 Voltage Compliance 630

9.4.3 Charge Injection and Clock Feedthrough 630

9.4.4 Random Mismatch between Up and Down Currents 632

9.4.5 Channel-Length Modulation 633

9.4.6 Circuit Techniques 634

9.5 Phase Noise in PLLs 638

9.5.1 VCO Phase Noise 638

9.5.2 Reference Phase Noise 643

9.6 Loop Bandwidth 645

9.7 Design Procedure 646

9.8 Appendix Ⅰ:Phase Margin of Type-Ⅱ PLLs 647

References 651

Problems 652

CHAPTER 10 INTEGER-N FREQUENCY SYNTHESIZERS 655

10.1 General Considerations 655

10.2 Basic Integer-N Synthesizer 659

10.3 Settling Behavior 661

10.4 Spur Reduction Techniques 664

10.5 PLL-Based Modulation 667

10.5.1 In-Loop Modulation 667

10.5.2 Modulation by Offset PLLs 670

10.6 Divider Design 673

10.6.1 Pulse Swallow Divider 674

10.6.2 Dual-Modulus Dividers 677

10.6.3 Choice of Prescaler Modulus 682

10.6.4 Divider Logic Styles 683

10.6.5 Miller Divider 699

10.6.6 Injection-Locked Dividers 707

10.6.7 Divider Delay and Phase Noise 709

References 712

Problems 713

CHAPTER 11 FRACTIONAL-N SYNTHESIZERS 715

11.1 Basic Concepts 715

11.2 Randomization and Noise Shaping 718

11.2.1 Modulus Randomization 718

11.2.2 Basic Noise Shaping 722

11.2.3 Higher-Order Noise Shaping 728

11.2.4 Problem of Out-of-Band Noise 732

11.2.5 Effect of Charge Pump Mismatch 733

11.3 Quantization Noise Reduction Techniques 738

11.3.1 DAC Feedforward 738

11.3.2 Fractional Divider 742

11.3.3 Reference Doubling 743

11.3.4 Multiphase Frequency Division 745

11.4 Appendix Ⅰ:Spectrum of Quantization Noise 748

References 749

Problems 749

CHAPTER 12 POWER AMPLIFIERS 751

12.1 General Considerations 751

12.1.1 Effect of High Currents 754

12.1.2 Efficiency 755

12.1.3 Linearity 756

12.1.4 Single-Ended and Differential PAs 758

12.2 Classification of Power Amplifiers 760

12.2.1 Class A Power Amplifiers 760

12.2.2 Class B Power Amplifiers 764

12.2.3 Class C Power Amplifiers 768

12.3 High-Efficiency Power Amplifiers 770

12.3.1 Class A Stage with Harmonic Enhancement 771

12.3.2 Class E Stage 772

12.3.3 Class F Power Amplifiers 775

12.4 Cascode Output Stages 776

12.5 Large-Signal Impedance Matching 780

12.6 Basic Linearization Techniques 782

12.6.1 Feedforward 783

12.6.2 Cartesian Feedback 786

12.6.3 Predistortion 787

12.6.4 Envelope Feedback 788

12.7 Polar Modulation 790

12.7.1 Basic Idea 790

12.7.2 Polar Modulation Issues 793

12.7.3 Improved Polar Modulation 796

12.8 Outphasing 802

12.8.1 Basic Idea 802

12.8.2 Outphasing Issues 805

12.9 Doherty Power Amplifier 811

12.10 Design Examples 814

12.10.1 Cascode PA Examples 815

12.10.2 Positive-Feedback PAs 819

12.10.3 PAs with Power Combining 821

12.10.4 Polar Modulation PAs 824

12.10.5 Outphasing PA Example 826

References 830

Problems 831

CHAPTER 13 TRANSCEIVER DESIGN EXAMPLE 833

13.1 System-Level Considerations 833

13.1.1 Receiver 834

13.1.2 Transmitter 838

13.1.3 Frequency Synthesizer 840

13.1.4 Frequency Planning 844

13.2 Receiver Design 848

13.2.1 LNA Design 849

13.2.2 Mixer Design 851

13.2.3 AGC 856

13.3 TX Design 861

13.3.1 PA Design 861

13.3.2 Upconverter 867

13.4 Synthesizer Design 869

13.4.1 VCO Design 869

13.4.2 Divider Design 878

13.4.3 Loop Design 882

References 886

Problems 886

INDEX 889